Hard to believe it's already 2023. Time flies when you’re having fun--and flies faster when you're being geeky.
A year or so ago I bought a nifty dev board--the TinyFPGA-BX. It gets good reviews, is well documented and relatively affordable ($38USD).
I figured this board would be a good starting point for learning, then using, FPGA's.
FPGAs are the cool ICs where you can create your own logic "from scratch". More here. But I know zilch about using these parts for AudioDiWhy. And I see a lot of cool FPGA use cases out there.
Almost zero knowledge is almost never good. Let's start trying to change that....
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The TinyFPGA is indeed....tiny.... |
The New Year started with a long weekend--which means--time to plug in this FPGA development board and install a Toolchain.
Hours of Fun!
But! The FPGA paradigm--hardware, software, all of it--was brand new for me--I needed guidance.
YouTube. Of course.
Shawn Hymel has an excellent (as always) video series about FPGA's, I started there.
Part I summarizes what FPGAs are and what they are commonly used for.
Part II goes over setting up the toolchain for Icestick....a development board very similar to the TinyFPGA-BX.
Good news….Both Icestick and TinyFPGA-BX are supported by APIO, a popular open source development platform for similar FPGA's. So I set out getting that going....Getting APIO working was the crux of the biscuit:
GO APIO!
I decided to install APIO on Windows, not Ubuntu. I thought it would be easier to find help if I got stuck--Shawn Hymel, as well as many other users online it seemed, used Windows for this toolchain.
Apio relies on Python.....I have Python 3.11 on my Windows system--the latest Python build as of this post.
I also installed Apio 0.6.7, not the latest Apio build. Shawn recommended using this older version.
For editing Apio project files I used Notepad++ which has syntax highlighting for Verilog--nice. Hint: if you use windows, run, don't walk, and get Notepad++. A million and one uses!
The proof of concept for the toolchain setup was to get get a blink going on the TinyFPGA but at a frequency faster than what is found in APIO's examples. Getting the basic blink should be easy--just load up APIO's example. But would it blink faster, Scotty?
TOOLCHAIN BASICS
I followed the setup steps in part II of Mr. Hymel's video--as well as steps found on the Apio website.
I won't repeat all that here, please watch the video and read the webpage.
I had to make a few changes; not sure if it was because I was not using an Icestick, rather a tinyFPGA; using Python 3.11 and not an older version; using an old version of Apio; or something else.
I was using a different FPGA dev board so I used this to initialize my FPGA board:
apio init --board TinyFPGA-BX
When I tried to build an the example Blinky project, Apio would throw an error I didn't record--something about an issue with Python's click module.
(Aside: Python click looks totally cool! I didn't know about this module! I am going to use it in future python projects....)
I guessed Python 3.11 was too new for the 0.6.7 version of Apio? Speculation....
Based on this hunch I upgraded to current Apio--cmd as local admin:
apio upgrade
It still didn't build!
It threw a different error; Apio told me to add tools-os-cad-suite. Perhaps this tool added functionailty needed for the TinyFPGA-BX. Not sure. Guessing still.
Again, I didn't record what I used to install this add-on, but the error message in Apio told me the exact syntax needed to install the tools-os-cad thingy.
Fixed?
Yes! Afterward I could "synthesize" a simple "Blinky" example:
apio build
Progress! Synthesis seemed to work!
UPLOADING BUILDS
Once the blinky code was synthesized--like C getting compiled I guessed? getting the dev board to eat code was next up.
Unlike the Icestick, the TinyFPGA-BX did not use an FTDI chip for USB to Serial. Instead it used tinyprog--some of the FPGA's gates do the USB to serial translation, not an external IC.
This must have been a ton of work for a very skilled FPGA developer....You can see python code used to call it here. Very cool stuff.
But the damn thing still wouldn't eat .v files:
--tinyfpga not found
However running tinyprog -m from elevated command prompt, yes, the dev board was recognized:
C:\Users\audiodiwhy\Dropbox\FPGA\apio-projects\tinyfpga-bx\BlinkyCL>tinyprog -m
[
{
"boardmeta": {
"name": "TinyFPGA BX",
"fpga": "ice40lp8k-cm81",
"hver": "1.0.0",
"uuid": "482fefbb-c6ce-4e08-aab8-84f55c23f788"
},
"bootmeta": {
"bootloader": "TinyFPGA USB Bootloader",
"bver": "1.0.1",
"update": "https://tinyfpga.com/update/tinyfpga-bx",
"addrmap": {
"bootloader": "0x000a0-0x28000",
"userimage": "0x28000-0x50000",
"userdata": "0x50000-0x100000"
}
},
"port": "COM3"
}
]
Hello?
I found a support page here--others with the same issue.
The workaround:
- run cmd as local administrator
- cd to the directory of the project
- run this instead from elevated cmd prompt:
tinyprog -c COM3 --program hardware.bin
COM3 had to match the com port found in the tinyprog -m output.
not sure why but--that worked!
MODIFYING THE .V FILE
In reboot mode the tinyFPGA had an LED-off fading to a LED-on, I wanted to create a more rapidly flashing LED to prove the toolchain worked.
Verilog isn't a programming language, rather a hardware description language. Either way, I knew zilch about how to do anything useful.
After making some random changes that made the LED go off (or change states so fast and slow it seemed like nothing was happening) I read a tiny sliver of how Verilog actually works. Imagine that!
I eventually stole the fix from another web page, here.
This .v file did the trick:
module Test (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
reg [19:0] counter = 0; // was [24:0]
always @(posedge CLK)
counter <= counter + 1;
assign LED = counter[19]; // was [19]
endmodule
From my limited understanding, [24:0] in the original Blinky sketch set up a 24 bit timer. I figured 19:0 would be faster since it's a 19 bit timer. It worked--the blinky blinked must faster.
UP AND OUT!
OK that's almost it for this time.
I have a working toolchain for FPGA!
I am still waiting for boards to come back from my loving sponsor, PCBWAY, (see, Wendy, I still got the plug in....) But they aren't due back for another few days.....
So more coding, less fumes? If I have time, I will try to learn a few more things about Verilog.
Onward!
Until then, have a Happy Geeky New Year!